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cmos 8-bit single chip microcomputer description the cxp82220/82224 is a cmos 8-bit single chip microcomputer integrating on a single chip an a/d converter, serial interface, timer/counter, time base timer, capture timer/counter, fluorescent display tube controller/driver, remote control reception circuit, ctl duty detection circuit, 14-bit pwm output, high-speed output circuit and other servo systems besides the basic configurations of 8-bit cpu, prom, ram, and i/o port. the cxp82220/82224 also provides power-on reset function and sleep/stop function that enables lower power consumption. features wide-range instruction system (213 instructions) to cover various types of data ?16-bit arithmetic/multiplication and division/boolean bit operation instructions minimum instruction cycle 400ns at 10mhz operation 122s at 32khz operation incorporated rom capacity 20k bytes (cxp82220) 24k bytes (cxp82224) incorporated ram capacity 704 bytes (including fluorescent display area) peripheral functions ?a/d converter 8 bits, 8 channels, successive approximation method (conversion time of 32s/10mhz) ?serial interface sio with 8-bit, 8-stage fifo incorporated for data use (auto transfer for 1 to 8 bytes), 1 channel 8-bit standard sio, 1 channel ?timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer 16-bit capture timer/counter, 32khz timer/counter ?fluorescent display tube controller/driver maximum of 384 segment display possible 1 to 16-digit dynamic display dimmer function high voltage drive output (40v) incorporated pull-down resistor (mask option) hardware key scan function maximum of 16 8 key matrix compatible ?remote control reception circuit incorporated noise elimination circuit incorporated 8-bit, 6-stage fifo for measurement data ?pwm output circuit 14 bits, 1 channel ?ctl duty detection circuit ?high-speed output circuit precision of 800ns at 10mhz, 4 outputs interruption 19 factors, 15 vectors, multi-interruption possible standby mode sleep/stop package 100-pin plastic qfp piggyback/evaluation chip cxp82200 100-pin ceramic qfp ?1 e92235a81-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. cxp82220/82224 100 pin qfp (plastic) structure silicon gate cmos ic
? 2 cxp82220/82224 a / d c o n v e r t e r f d p c o n t r o l l e r / d r i v e r 1 4 b i t p w m g e n e r a t o r c t l d u t y d e t r e m o c o n s e r i a l i n t e r f a c e u n i t 1 8 b i t t i m e r / c o u n t e r 0 8 b i t t i m e r 1 1 6 b i t c a p t u r e t i m e r / c o u n t e r 2 r a m 8 0 b y t e s f i f o s e r i a l i n t e r f a c e u n i t 0 f i f o i n t e r r u p t c o n t r o l l e r s p c 7 0 0 c p u c o r e r o m 2 0 k b y t e s ( c x p 8 2 2 2 0 ) 2 4 k b y t e s ( c x p 8 2 2 2 4 ) c l o c k g e n . / s y s t e m c o n t r o l r a m 7 0 4 b y t e s 2 2 2 2 2 p r e s c a l e r / t i m e b a s e t i m e r 3 2 k h z t i m e r / c o u n t e r r e a l t i m e p u l s e g e n e r a t o r c h 0 c h 1 2 8 8 8 2 4 a v r e f a v s s p e 0 / e c 0 / i n t 0 p e 1 / e c 1 / i n t 1 p e 2 / i n t 2 p e 3 / i n t 3 / n m i v s s v d d r s t x t a l e x t a l t x t e x p g 0 / r t o 0 t o p g 3 / r t o 3 p o r t a p o r t b p o r t c p o r t d p o r t e p o r t f p o r t g p o r t h p o r t i 4 8 8 8 8 8 8 8 6 2 p a 0 / a n 0 t o p a 7 / a n 7 t 0 t o t 7 t 8 / s 3 1 t o t 1 5 / s 2 4 p d 0 / s 0 t o p i 7 / s 2 3 v f d p p e 6 / p w m p e 5 / c t l p e 7 / d d o p e 4 / r m c p b 1 / c s 0 p b 3 / s i 0 p b 4 / s o 0 p b 2 / s c k 0 p b 6 / s i 1 p b 7 / s o 1 p b 5 / s c k 1 p e 0 / i n t 0 / e c 0 p e 7 / t o p b 0 / c i n t p e 1 / i n t 1 / e c 1 p a 0 t o p a 7 p c 0 t o p c 7 p d 0 t o p d 7 p e 0 t o p e 5 p e 6 t o p e 7 p f 0 t o p f 7 p g 0 t o p g 7 p h 0 t o p h 7 p i 0 t o p i 7 7 p b 0 t o p b 6 p b 7 block diagram
? 3 cxp82220/82224 p e 1 / e c 1 / i n t 1 p e 2 / i n t 2 p e 3 / i n t 3 / n m i p e 4 / r m c p e 5 / c t l p e 6 / p w m p e 7 / t o / d d o / a d j p b 0 / c i n t p b 1 / c s 0 p b 2 / s c k 0 p b 3 / s i 0 p b 4 / s o 0 p b 5 / s c k 1 p b 6 / s i 1 p b 7 / s o 1 p c 0 / k r 0 p c 1 / k r 1 p c 2 / k r 2 p c 3 / k r 3 p c 4 / k r 4 p c 5 / k r 5 p c 6 / k r 6 p c 7 / k r 7 p h 0 p h 1 p h 2 p h 3 p h 4 p h 5 p h 6 t 7 t 8 / s 3 1 t 9 / s 3 0 t 1 0 / s 2 9 t 1 4 / s 2 5 t 1 5 / s 2 4 p i 7 / s 2 3 p i 6 / s 2 2 p i 5 / s 2 1 p i 4 / s 2 0 p i 3 / s 1 9 p i 2 / s 1 8 p i 0 / s 1 6 p f 7 / s 1 5 p f 6 / s 1 4 p f 5 / s 1 3 p f 4 / s 1 2 p f 3 / s 1 1 p f 2 / s 1 0 p f 1 / s 9 p f 0 / s 8 p d 7 / s 7 p d 6 / s 6 p d 5 / s 5 p d 4 / s 4 p d 3 / s 3 p h 7 p a 0 / a n 0 p a 1 / a n 1 p a 2 / a n 2 p a 3 / a n 3 p a 4 / a n 4 p a 5 / a n 5 r s t e x t a l x t a l v s s t x t e x p a 6 / a n 6 p a 7 / a n 7 a v r e f a v s s p d 0 / s 0 p d 1 / s 1 p d 2 / s 2 p g 1 / r t o 1 p e 0 / e c 0 / i n t 0 p g 7 p g 5 p g 4 p g 3 / r t o 3 p g 2 / r t o 2 p g 0 / r t o 0 v s s n c v d d v f d p t 0 t 1 t 2 t 3 t 4 t 5 t 6 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 7 0 6 9 6 8 6 7 6 3 6 4 6 5 6 6 6 1 6 2 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 8 1 8 2 8 3 8 4 8 8 8 7 8 6 8 5 8 9 9 0 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 1 9 2 9 3 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 1 p i 1 / s 1 7 t 1 2 / s 2 7 t 1 3 / s 2 6 t 1 1 / s 2 8 p g 6 note) nc (pin 90) must be connected to v dd. pin assignment (top view)
cxp82220/82224 pin description ? 4 (port a) 8-bit i/o port. i/o can be set in a unit of single bit . (8 pins) (port b) 8-bit i/o port. i/o for lower 7 bits can be set in a unit of single bit. uppermost bit (pb7) is for output only. (8 pins) (port c) 8-bit i/o port. i/o can be set in a unit of single bits. capable of driving 12ma synk current. (8 pins) (port d) 8-bit output port. (8 pins) (port e) 8-bit port. lower 6 bits are for inputs; upper 2 bits are for outputs. (8 pins) (port f) 8-bit output port. (8 pins) (port g) 8-bit i/o port. i/o can be set in a unit of single bit. data for the lower 4 bits are gated with the contents of rto or or-gate output. (8 pins) analog inputs to a/d converter. (8 pins) external capture input to 16bittimer/counter. chip select input for serial interface (ch0). serial clock i/o (ch0). serial data input (ch0). serial data output (ch0). serial clock i/o (ch1). serial data input (ch1). serial data output (ch1). serves as key return inputs when operating key scan with fdp segment signal. fdp segment signal outputs. inputs for external interruption request. (4 pins) remote control reception circuit input. input for ctl duty ditection circuit. 14-bit pwm output. output for the 16-bit timer/counter rectangular waves, ctu duty detection, and 32khz oscillation frequuency demultiplication. outputs for real-time pulse generator (rtg). functions as high-precision, real-time pulse output port. (4 pins) symbol i/o functions pa0/an0 to pa7/an7 pb0/cint pb1/cs0 pb2/sck0 pb3/si0 pb4/so0 pb5/sck1 pb6/si1 pb7/so1 pc0/kr0 to pc7/kr7 pd0/s0 to pd7/s7 pe0/int0/ec0 pe1/int1/ec1 pe2/int2 pe3/int3/nmi pe4/rmc pe5/ctl pe6/pwm pe7/to/ddo/ adj pf0/s8 to pf7/s15 pg0/rto0 to pg3/rto3 pg4 to pg7 i/o/ analog input i/o/input i/o/input i/o/i/o i/o/input i/o/output i/o/i/o i/o/input output/output i/o/input output/output input/input/input input/input/input input/input input/input/input input/input input/input output/output output/output/ output/output output/output i/o/output i/o external event inputs for timer/counter. (2 pins) non-maskable interruption request input. fdp segment signal outputs.
? 5 cxp82220/82224 (port h) 8-bit i/o port. i/o can be set in a unit of single bit. (8 pins) (port i) 8-bit output ports. fdp segment signal outputs. (8 bits) outputs for fdp timing (digit) signals/segment signals. fdp timing signal outputs. fdp voltage supply when incorporated resistor is set by mask option. crystal connectors for system clock oscillation. when the clock is supplied externally, input to extal; opposite phase clock should be input to xtal. crystal connectors for 32khz timer/counter clock oscillation. set 32khz crystal oscillator between tex and tx. for usage as event input, attach clock source to tex, and open tx. low-level active, system reset. nc. under normal operation, connect to v dd . reference voltage input for a/d converter. a/d converter gnd. positive power supply. gnd. symbol i/o functions ph0 to ph7 pi0/s16 to pi7/s23 t8/s31 to t15/s24 t0 to t7 v fdp extal xtal tex tx rst nc av ref av ss v dd v ss i/o output/output output/output output input output input output input input
? 6 cxp82220/82224 when reset pin circuit format input/output circuit formats for pins i p r d ( p o r t b ) d a t a b u s p o r t b d i r e c t i o n p o r t b o u t p u t s e l e c t i o n " 0 " w h e n r e s e t s c k i n s c h m i t t i n p u t p o r t b d a t a " 0 " w h e n r e s e t s c k o u t o u t p u t e n a b l e hi-z hi-z hi-z pb0/cint pb1/cs0 pb3/si0 pb6/si1 pb2/sck0 pb5/sck1 port b port b 2 pins port a i p i n p u t p r o t e c t i o n c i r c u i t r d ( p o r t a ) d a t a b u s p o r t a d i r e c t i o n p o r t a d a t a " 0 " w h e n r e s e t p o r t a i n p u t s e l e c t i o n " 0 " w h e n r e s e t a / d c o n v e r t e r i n p u t m u l t i p l e x e r i p r d ( p o r t b ) d a t a b u s p o r t b d i r e c t i o n p o r t b d a t a " 0 " w h e n r e s e t c i n t c s 0 s i 0 s i 1 s c h m i t t i n p u t pa0/an0 to pa7/an7 8 pins 4 pins
? 7 cxp82220/82224 when reset pin circuit format i p r d ( p o r t b ) d a t a b u s p o r t b d i r e c t i o n p o r t b o u t p u t s e l e c t i o n " 0 " w h e n r e s e t p o r t b d a t a " 0 " w h e n r e s e t s o o u t p u t e n a b l e port b port c port e 1 pin high level hi-z hi-z pb4/so0 pb7/so1 1 pin 8 pins hi-z pc0/kr0 to pc7/kr7 6 pins pe0/ec0/int0 pe1/ec1/int1 pe2/int2 pe3/int3/nmi pe4/rmc pe5/ctl port b i p r d ( p o r t c ) d a t a b u s p o r t c d i r e c t i o n p o r t c d a t a " 0 " w h e n r e s e t k e y i n p u t s i g n a l * l a r g e c u r r e n t d r i v e o f 1 2 m a p o s s i b l e * r d ( p o r t e ) i p e c 0 / i n t 0 e c 1 / i n t 1 i n t 2 i n t 3 / n m i r m c c t l d a t a b u s s c h m i t t i n p u t r d ( p o r t b ) d a t a b u s p o r t b o u t p u t s e l e c t i o n " 1 " w h e n r e s e t p o r t b d a t a " 1 " w h e n r e s e t s o o u t p u t e n a b l e i n t e r n a l r e s e t s i g n a l * * p u l l - u p t r a n s i s t o r a p p r o x . 1 0 k w
? 8 cxp82220/82224 when reset pin circuit format i p r d ( p o r t g ) d a t a b u s p o r t g d i r e c t i o n p o r t g d a t a " 0 " w h e n r e s e t r t o d a t a " 0 " w h e n r e s e t r d ( p o r t e ) d a t a b u s p o r t e o u t p u t s e l e c t i o n " 1 " w h e n r e s e t p o r t e d a t a " 0 " w h e n r e s e t * * a d j s i g n a l i s a f r e q u e n c y d e m u l t i p l i c a t i o n o u t p u t f o r 3 2 k h z o s c i l l a t i o n f r e q u e n c y a d j u s t m e n t . a d j 2 k c a n b e u s e d f o r b u z z e r o u t p u t . p o r t e o u t p u t s e l e c t i o n p o r t e o u t p u t s e l e c t i o n 0 1 2 3 m p x t o d d o a d j 1 6 k a d j 2 k o u t p u t e n a b l e * " 0 0 " w h e n r e s e t r d ( p o r t e ) d a t a b u s p o r t e o u t p u t s e l e c t i o n " 1 " w h e n r e s e t p o r t e d a t a " 0 " w h e n r e s e t p w m port e 1 pin high level hi-z pe6/pwm pe7/to/ ddo/adj port g 1 pin 4 pins high level pg0/rto0 to pg3/rto3 port e
? 9 cxp82220/82224 v f d p * r d ( p o r t d , f , o r i ) d a t a b u s " 0 " w h e n r e s e t p o r t d , f , o r i d a t a ( " 0 " w h e n r e s e t ) s e g m e n t o u t p u t d a t a o u t p u t s e l e c t i o n c o n t r o l s i g n a l * h i g h v o l t a g e d r i v e t r a n s i s t o r m a s k o p t i o n p u l l - d o w n r e s i s t o r o p 24 pins hi-z or low level (when pd resistance is added) oscillation when reset pd0/s0 to pd7/s7 pf0/s8 to pf7/s15 pi0/s16 to pi7/s23 t15/s24 to t8/s31 t0 to t7 16 pins 2 pins extal xtal hi-z or low level (when pd resistance is added) port d port g port h port f port i pin circuit format v f d p * ( " 0 " w h e n r e s e t ) s e g m e n t o u t p u t d a t a o u t p u t s e l e c t i o n c o n t r o l s i g n a l * h i g h v o l t a g e d r i v e t r a n s i s t o r m a s k o p t i o n p u l l - d o w n r e s i s t o r o p i p i p e x t a l x t a l d i a g r a m s h o w s c i r c u i t c o m p o s i t i o n d u r i n g o s c i l l a t i o n . f e e d b a c k r e s i s t o r i s r e m o v e d d u r i n g s t o p . hi-z 12 pins pg4 to pg7 ph0 to ph7 i p r d ( p o r t g o r p o r t h ) d a t a b u s p o r t g o r p o r t h d i r e c t i o n p o r t g o r p o r t h d a t a " 0 " w h e n r e s e t
? 10 cxp82220/82224 2 pins oscillation tex tx i p i p t e x t x w h e n t h e o p e r a t i o n o f t h e o s c i l l a t i o n c i r c u i t i s s t o p p e d b y t h e s o f t w a r e , t h e f e e d b a c k r e s i s t o r i s r e m o v e d , a n d t e x a n d t x b e c o m e " l o w " l e v e l a n d " h i g h " l e v e l r e s p e c t i v e l y . d i a g r a m s h o w s c i r c u i t c o m p o s i t i o n d u r i n g o s c i l l a t i o n . 1 pin low level rst m a s k o p t i o n i p s c h m i t t i n p u t p u l l - u p r e s i s t o r o p when reset pin circuit format
? 11 cxp82220/82224 * 1 v in and v out must not exceed v dd + 0.3v. * 2 specifies output current of general-purpose l/o ports. * 3 the large current drive transistor is the n-ch transistor of port c (pc). note) usage exceeding absolute maximum ratings may permanently impair the lsi. normal operation should be conducted under the recommended operating conditions. exceeding these conditions may adversely affect the reliability of the lsl. supply voltage input voltage output voltage display output voltage high level output current high level total output current low level output current low level total output current operating temperature storage temperature allowable power dissipation v dd av ss v in v out v od i oh i odh1 i odh2 i oh i odh i ol i olc i ol topr tstg p d as p channel transistor is open drain, v dd is reference. all pins excluding display outputs * 2 (value per pin) display outputs s0 to s23 (value per pin) display outputs t0 to t7, and t8/s31 to t15/s24 (value per pin) total for all pins excluding display outputs total for all display outputs port 1 large current port 1 * 3 total for all output pins item symbol rating unit remarks absolute maximum ratings (vss = 0v reference) ?.3 to +7.0 ?.3 to +0.3 ?.3 to +7.0 * 1 ?.3 to +7.0 * 1 v dd ?40 to v dd + 0.3 ? ?5 ?5 ?0 ?00 15 20 100 ?0 to +75 ?5 to +150 600 v v v v v ma ma ma ma ma ma ma ma c c mw
? 12 cxp82220/82224 high level input voltage low level input voltage operating temperature supply voltage 5.5 5.5 5.5 5.5 v dd v dd v dd + 0.3 0.3v dd 0.2v dd 0.4 +75 v v v v v v c v item symbol min. max. unit remarks 4.5 3.5 2.7 2.5 0.7v dd 0.8v dd v dd ?0.4 0 0 ?.3 ?0 v ih v ihs v ihex v il v ils v ilex topr high-speed mode guaranteed operation range low-speed mode guaranteed operation range guaranteed operation range with tex clock guaranteed data hold range during stop * 1 hysteresis input * 2 extal * 3 * 1 hysteresis input * 2 extal * 3 v dd * 1 value for each pin of normal input ports (pa, pb3, pb4, pb6, pc, pg, ph). * 2 value of the following pins: rst, cint, cs0, sck0, sck1, ec0/int0, ec1/int1, int2, int3/nmi, rmc, ctl. * 3 specifies only during external clock input. recommended operating conditions (vss = 0v reference)
? 13 cxp82220/82224 v dd = 4.5v, i oh = ?.5ma v dd = 4.5v, i oh = ?.2ma v dd = 4.5v, i ol = 1.8ma v dd = 4.5v, i ol = 3.6ma v dd = 4.5v, i ol = 12.0ma v dd = 5.5v, v ih = 5.5v v dd = 5.5v, v il = 0.4v v dd = 5.5v, v ih = 5.5v high level output voltage 4.0 3.5 0.5 ?.5 0.1 ?.1 ?.5 ? ?0 60 v v v v v a a a a a ma ma a k a ma a ma a a pf pc extal tex rst * 1 item symbol pins conditions min. v dd i dd1 i oh i lol i dd2 i dds1 i dds2 i dds3 c in v oh v ol i ihe i ile i iht i ilt i ilr low level output voltage input current typ. 0.4 0.6 1.5 40 ?0 10 ?0 ?00 ?0 270 10 40 100 8 30 10 20 max. unit dc characteristics electrical characteristics (ta = ?0 to +75 c, vss = 0v reference) v dd = 5.5v, 10mhz crystal oscillation (c 1 = c 2 = 15pf) v dd = 3v, 32khz crystal oscillation (c 1 = c 2 = 47pf) v dd = 5.5v, 10mhz crystal oscillation (c 1 = c 2 = 15pf) v dd = 3v, 32khz crystal oscillation (c 1 = c 2 = 47pf) supply current * 3 input capacity v dd = 5.5v, v il = 0.4v v dd = 4.5v, v oh = v dd ?2.5v v dd = 5.5v v ol = v dd ?35v v fdp = v dd ?35v high-speed mode operation (1/2 frequency demultiplier clock) stop mode v dd = 5.5v, termination of 10mhz and 32khz crystal oscillation clock 1mhz 0v for all pins excluding measured pins display output current i iz i/o leakage current open drain output leakage current (p-ch tr in off state) s0 to s23 s24/t15 to s31/t8 t0 to t7 s0 to s23 s24/t15 to s31/t8 t0 to t7 r l v dd = 5v v fdp = v dd ?35v v dd = 5.5v v i = 0, 5.5v pull-down resistance * 2 s0 to s23 s24/t15 to s31/t8 t0 to t7 pa to pc, pe, pg, ph, rst * 1 100 20 35 1.2 9 10 pa, pb, pc,pe6, pe7, pg, ph pins other than s0 to s31, t0 to t7, pb7, pe6,pe7,av ref , av ss , v fdp , v dd , v ss sleep mode * 1 rst specifies the input current when pull-up resistance has been selected; leakage current when no resisance has been selected. * 2 when incorporated pull-down resistance has been selected through mask option. * 3 when all pins are open.
? 14 cxp82220/82224 * 1 t sys indicates the three values below according to the upper two bits (cpu clock selection) of the clock control register (address: 00fe h ). t sys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") e x t a l t x h t x l t c f t c r 0 . 4 v v d d 0 . 4 v 1 / f c a a a a a a a a a a a a a a a e x t e r n a l c l o c k e x t a l x t a l 7 4 h c 0 4 a a a a a a a a a a a a c r y s t a l o s c i l l a t i o n c e r a m i c o s c i l l a t i o n e x t a l x t a l c 1 c 2 a a a a a a a a a a a a a a a 3 2 k h z c l o c k a p p l i e d c o n d i t i o n c r y s t a l o s c i l l a t i o n t e x t x c 1 c 2 ac characteristics (1) clock timing system clock frequency system clock input pulse width system clock input rise time, fall time event count input clock pulse width event count input clock rise time, fall time system clock frequency event count input clock input pulse width event count input clock rise time,fall time f c t xl , t xh t cr , t cf t eh , t el t er , t ef f c t tl , t th t tr , t tf xtal extal extal extal ec0 ec1 ec0 ec1 tex tx tex tex mhz ns ns ns ms khz s ms item symbol pins conditions unit fig. 1, fig. 2 fig. 1, fig. 2 external clock drive fig. 1, fig. 2 external clock drive fig. 3 fig. 3 v dd = 2.7 to 5.5v fig. 2 (32khz clock applied condition) fig. 3 fig. 3 typ. 32.768 min. 1 37.5 t sys + 50 * 1 10 max. 10 200 20 20 (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) fig. 1. clock timing fig. 2. clock applied conditions
? 15 cxp82220/82224 input mode output mode input mode output mode sck0 input mode sck0 output mode sck0 input mode sck0 output mode sck0 input mode sck0 output mode chip select transfer mode (sck0 = output mode) chip select transfer mode (sck0 = output mode) chip select transfer mode chip select transfer mode chip select transfer mode note 1) t sys indicates the three values below according to the upper two bits (cpu clock selection) of the clock control register (address: 00fe h ). t sys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") note 2) the load condition for the sck0 output mode, so0 output delay time is 50pf + 1ttl. (2) serial transfer (ch0) (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss=0v reference) item cs0 ? sck0 delay time cs0 - ? sck0 float delay time cs0 ? so0 delay time cs0 - ? so0 float delay time cs0 high level width sck0 cycle time sck0 high, low level width si0 input setup time (for sck0 - ) si0 input hold time (for sck0 - ) sck0 ? so0 delay time t dcsk t dcskf t dcso t dcsof t whcs t kcy t kh , t kl t sik t ksi t kso sck0 sck0 so0 so0 cs0 sck0 sck0 si0 si0 so0 ns ns ns ns ns symbol pin min. t sys + 200 t sys + 200 t sys + 200 t sys + 200 t sys + 200 2 t sys + 200 16000/fc t sys + 100 8000/fc ?50 100 200 t sys + 200 100 ns ns ns ns ns ns ns ns ns ns t sys + 200 100 max. unit condition t e x e c 0 e c 1 t e h t e l t e f t e r 0 . 2 v d d 0 . 8 v d d t t h t t l t t f t t r fig. 3. event count clock timing
cxp82220/82224 fig. 4. serial transfer ch0 timing c s 0 s c k 0 0 . 2 v d d 0 . 8 v d d t w h c s t d c s k t d c s k f 0 . 8 v d d 0 . 2 v d d 0 . 8 v d d t k c y t k l t k h 0 . 8 v d d 0 . 2 v d d s i 0 t s i k t k s i i n p u t d a t a t d c s o t k s o t d c s o f o u t p u t d a t a 0 . 8 v d d 0 . 2 v d d s o 0 ? 16
? 17 cxp82220/82224 serial transfer (ch1) (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) item symbol pin min. max. condition sck1 cycle time sck1 high, low level width si1 input setup time (for sck1 - ) si1 input hold time (for sck1 - ) sck1 ? so1 delay time t kcy t kh , t kl t sik t ksi t kso sck1 sck1 si1 si1 so1 input mode output mode input mode output mode sck1 input mode sck1 output mode sck1 input mode sck1 output mode sck1 input mode sck1 output mode 1000 16000/fc 400 8000/fc ?50 100 200 200 100 200 100 unit ns ns ns ns ns ns ns ns ns ns note) the load condition for the sck1 output mode, so1 output delay time is 50pf + 1ttl. fig. 5. serial transfer ch1 timing s c k 1 s i 1 s o 1 t k c y t k l t k h 0 . 2 v d d 0 . 8 v d d t s i k t k s i t k s o i n p u t d a t a o u t p u t d a t a 0 . 2 v d d 0 . 8 v d d 0 . 2 v d d 0 . 8 v d d
? 18 cxp82220/82224 (3) a/d converter characteristics v zt * 1 v ft * 2 t conv t samp v ref v ian i ref i refs ta = 25 c v dd = av dd = 5.0v v dd = avss = 0v operation mode sleep mode stop mode 32khz operation mode av ref ?0 4930 160/f adc * 3 12/f adc * 3 v dd ?0.5 0 item symbol pin condition min. typ. max. unit bits resolution linearity error zero transition voltage full-scale transition voltage conversion time sampling time reference input voltage analog input voltage av ref current (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, av ref = 4.0 to av dd , vss = avss = 0v reference) 8 5 150 5120 v dd av ref 1.0 10 70 5050 0.6 lsb mv mv s s v v ma a a n a l o g i n p u t l i n e a r i t y e r r o r 0 0 h 0 1 h f e h f f h d i g i t a l c o n v e r s i o n v a l u e v z t v f t fig. 6. definitions of a/d converter terms av ref an0 to an7 * 1 v zt : value at which the digital conversion value changes from 00 h to 01 h and vice versa. * 2 v ft : value at which the digital conversion value changes from fe h to ff h and vice versa. * 3 f adc indicates the below values due to adc operation clock selection (adcs: bit 6 of address 00f9 h ). during ps2 selection, f adc = fc/2 during ps1 selection, f adc = fc
? 19 cxp82220/82224 external interruption high, low level width reset input low level width int0 int1 int2 nmi/int3 rst 1 8/fc s s item symbol pins condition min. max. unit t ih t il t rsl (4) interruption, reset input (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) 0 . 8 v d d 0 . 2 v d d t i h t i l i n t 0 i n t 1 i n t 2 n m i / i n t 3 ( n m i s p e c i f i e s o n l y f o r t h e f a l l i n g e d g e ) t i l t i h fig. 7. interruption input timing t r s l 0 . 2 v d d r s t fig. 8. rst input timing 0 . 2 v d d 0 . 8 v d d t c t h t c t l c t l fig. 9. other timing clk input high, low level width t cth , t ctl ctl item symbol pin condition min. max. unit ns (5) others (ta = ?0 to +75 c, v dd = 4.5 to 5.0v, v ss = 0v reference) t sys = 2000/fc t sys + 200
? 20 cxp82220/82224 appendix a a a a a a a a a a a a e x t a l x t a l c 1 c 2 ( i ) m a i n c l o c k a a a a a a a a a a a a e x t a l x t a l c 2 ( i i ) m a i n c l o c k a a a a a a a a a a a a t e x t x c 1 c 2 r d ( i i i ) s u b c l o c k c 1 manufacturer murata mfg co., ltd river eletec corporation kinseki ltd. csa4.19mg csa8.00mg csa10.0mt cst4.19mgw * cst8.00mtw * cst10.00mtw * hc-49/u03 hc-49/u (-s) model fc (mhz) 4.19 8.00 10.00 4.19 8.00 10.00 4.19 8.00 10.00 4.19 8.00 10.00 30 15 27 30 15 27 c 1 (pf) c 2 (pf) circuit example (i) (ii) (i) those marked with an asterisk ( * ) signify types with built-in ground capacitance (c 1 , c 2 ). item contents reset pin pull-up resistor high voltage drive output port pull-down non-existent non-existent existent existent mask option table fig. 10. recommended oscillation circuit
? 21 cxp82220/82224 package outline unit: mm s o n y c o d e e i a j c o d e j e d e c c o d e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n s o l d e r p l a t i n g 4 2 / c o p p e r a l l o y p a c k a g e s t r u c t u r e 2 3 . 9 0 . 4 q f p - 1 0 0 p - l 0 1 1 0 0 p i n q f p ( p l a s t i c ) 2 0 . 0 0 . 1 + 0 . 4 0 . 1 5 0 . 0 5 + 0 . 1 1 5 . 8 0 . 4 1 7 . 9 0 . 4 1 4 . 0 0 . 1 + 0 . 4 2 . 7 5 0 . 1 5 + 0 . 3 5 a 0 . 6 5 m 0 . 1 3 q f p 1 0 0 - p - 1 4 2 0 1 . 7 g 1 1 0 0 8 1 8 0 5 1 5 0 3 1 3 0 0 . 3 0 . 1 + 0 . 1 5 d e t a i l a 0 t o 1 0 0 . 8 0 . 2 ( 1 6 . 3 ) 0 . 1 5 0 . 1 0 . 0 5 + 0 . 2

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